Highly integrated semiconductor chips, such as LSI and VLSI chips are usually electrically connected to a designated package substrate utilizing either wire bonding or what is referred to as "flip chip" bonding procedures, the substrate and chip thereby forming an electronic package. FIG. 5 of the drawings is a view showing one example of such a substrate-chip package assembly. The substrate (40) is may also be referred to as a module substrate, and may be of conventional fiberglass reinforced resin material (a/k/a FR4), or ceramic, as is known. The substrate typically includes a wiring pattern having several electrical conductors (a/k/a electrodes) as part thereof, the chip being coupled to these. The conductors to which the chips are directly coupled are understood to be below the chip in FIG. 5 and thus hidden. These conductors "fan out" in FIG. 5 as part of this wiring pattern to a plurality of peripheral conductors which in turn are to be coupled to associated, respective conductors of a second substrate, e.g., a printed circuit board.
These outer conductors, as mentioned, are electrically connected to respective conductors on the printed circuit board, usually with a plurality of lead wires. This circuit board and wires are not shown in FIG. 5. In other words, both ends of each lead wire are disposed in such a manner that the ends extend around the peripheral side of the package substrate. These ends of the lead wire are typically connected with solder or a conductive bonding agent, the connections being carried out on a wire-by-wire basis which serves to electrically connect and simultaneously mechanically fix the substrate onto the printed circuit board.
One example of such a lead wire connection is disclosed in Japanese PUPA 3-201545. In this example, the lead wire has a circular projection with respect to the plane of the bottom part of the chip's substrate, the projection serving to electrically connect with the conductor (electrode) on the associated printed circuit board. The conductor is electrically connected to the lead wire with a conductive bonding agent.
In addition, IBM Technical Disclosure Bulletin, Vol. 30, No. 3, (August, 1987), pp. 1250, 1241, also discloses a semiconductor device which uses a lead wire for electrically connecting an electrode of a substrate having a chip mounted thereon to an external electrode. In this case, the lead wire has a substantially circular projection with respect to the plane of the bottom part of the substrate in such a manner that the lead wire covers the side of the external periphery of the substrate, the projection serving to electrically connect with the electrode part on the printed circuit board. In this case the lead wire is fixed to the substrate at two positions, the top of the substrate and the bottom thereof.
As highly integrated IC chips such as LSI and VLSI chips have several electrical input/output (I/O) locations, the number of corresponding electrodes on the chip--s substrate must accommodate this number of I/O locations. The total number of these may be several hundred, depending on the operational characteristics of the package. As understood, the size of the chip's substrate is restricted by the size of the printed circuit board on which this substrate is mounted. Both are preferably as small as possible to meet current design objectives toward miniaturization. Consequently, in accordance with the increase in the integration of such chips, the spaces between substrate electrodes have narrowed substantially. Likewise, the spaces between lead wires has been reduced, and the corresponding thickness of the lead wires also reduced.
Reducing lead wire thicknesses and spacings has resulted in various problems. For example, the strength of the individual lead wires has decreased thereby allowing easier deformation thereof by external force. Consequently, in the process of placing the lead wire onto the substrate, adjacent lead wires may come into contact with one another. In addition, electrical connection of several lead wires with electrodes on a printed circuit board wherein the lead wires include circular projections (as described above) may result in an irregular height pattern for these projections with respect to the plane of the bottom of the substrate, thereby presenting the possibility that one or more of these wires may not be electrically connected with its associated electrode on the printed circuit board. The methods described in the above PUPA 3-201545 and IBM Technical Disclosure Bulletin, do not address an effective means of overcoming the above problems.
Japanese PUPA 4-79472 discloses a lead wire fixed with a tape in an attempt to eliminate irregularity in the various spacings between adjacent lead wires. However, the lead wire in this case is manufactured integrally with the electronic component in advance. One end of tile lead line extending from the side of the electronic component is electrically connected with the electrode on the printed circuit board with solder.